This invention relates to the fabrication of microminiature devices and, more particularly, to an automated, high-speed electron beam apparatus and method for making such devices.
It has long been known that the high-resolution and excellent depth-of-focus capabilities of an electron beam make it a practical tool for inclusion in an automated system for making microminiature electronic devices. The electron beam is controlled in a highly accurate and high-speed manner to expose an electron-resist-coated material as a step in the fabrication of extremely small and precise low-cost integrated circuits.
Although an electron beam can be deflected and blanked in a high-speed manner, the scan area over which the beam is capable of being accurately deflected is relatively small. A basic problem presented, therefore, is how to utilize an electron beam which has a small-area scan field to rapidly and accurately expose relatively large chip pattern areas.
In addition to the need for exposing large areas, large densities of circuits are desired on semiconductor chips. The trend in the industry has been towards a greater number of circuits per unit of area and towards smaller circuit elements. With this trend, it has become increasingly possible to integrate an entire system or subsystem on one or a relatively few number of semiconductor chips.
In order to accommodate the greater density of circuits and to obtain the accuracy required for smaller circuit elements, electron beam systems are employed to scan chip patterns or portions of chip patterns each covering an area which is equal to or less than the scan field area which can be accurately scanned by the electron beam.
When the chip pattern to be scanned covers an area greater than the area which can be accurately scanned by the electron beam, the chip pattern is divided into partitions where each partition has an area which is small enough to fit within the scan field of the electron beam. The partitions are then scanned one at a time. After scanning each partition, the work piece (wafer or other material to be scanned) is moved so that the electron beam scan field is relocated for scanning the next adjacent partition. In this manner, the entire chip pattern is scanned one partition at a time.
In order that the composite chip pattern be accurately scanned, each partition must be accurately scanned. Furthermore, adjacent partitions must be properly aligned (that is, properly registered) with respect to each other. Failure to have proper registration means that circuit elements crossing the boundry between partitions will be misaligned. This problem of partition alignment is a problem of registering the electron beam scan field on the work piece each time the work piece is moved.
Problems arise in connection with the registration of the scan field particularly when circuit elements having critical dimensions are located at or near the boundary between adjacent partitions. If a circuit element having a critical dimension is located across a partition boundary, portions of the circuit element will normally be scanned at two different times with two different positions of the work piece relative to the electron beam scan field.
If the electron beam scan field position at one location of the work piece is misaligned relative to its position at an adjacent position of the work piece, then an error due to the misalignment will be introduced into the scanning of the circuit element crossing the boundary. If the magnitude of the misalignment is large with respect to critical dimensions of the circuit element being scanned, the circuit element will be significantly malformed.
The problem of how to accurately register and reregister the scan field on a work piece is well known. Many different solutions for this problem have been proposed and have been employed with various degrees of success. Many of these solutions employ alignment marks within each partition for use in connection with registering the scan field when the work piece is moved. While the use of alignment marks in various forms is useful and desirable, there is still a need for an improved method and apparatus for avoiding the problems caused by misalignment of adjacent partitions.
In accordance with the above background of the invention, it is an object of the present invention to provide an improved electron beam apparatus and method for successively scanning smaller partitions to form a larger composite chip pattern.